What does 'number of jobs' mean in the synthesis pop-up windows?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Is it possible to gray code 0 to 5 (not a power of 2)?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What does 'rise continuously' mean?
A place to ask questions, discuss topics and share projects related to Electrical Engineering.
What does the 'TM' mark mean here?
A place to ask questions, discuss topics and share projects related to Electrical Engineering.
What does 'internal core logic' mean?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What XDC codes/tcl codes should we use to tell Vivado to do a proper timing analysis or constraint on a time borrowing design?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What XDC codes/tcl codes should we use to tell Vivado to do a proper timing analysis or constraint on a time borrowing design?
A subreddit for the discussion of all things related to the creation (not usage of!) integrated circuits, both circuit- and process-level.
Which user guide should I look up if I wanna know if a certain FPGA chip has something like a built-in flash memory so that I don't need an external one?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Which user guide should I look up if I wanna know if a certain FPGA has something like a built-in flash memory so that I don't need an external one?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Which user guide should I look up if I wanna know if a certain FPGA chip has something like a built-in flash memory so that I don't need an external one?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Which user guide should I consult?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Which user guide should I look up for this info?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Which user guide should I look up for this info?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Is Xilinx Synthesis Technology (XST) only available in ISE, not in Vivado?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What XDC codes/tcl codes should we use to tell Vivado to do a proper timing analysis or constraint on our time borrowing design?
What is the source of this clock signal?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
Which user guide is "the respective 7 series FPGAs data sheet"?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What does 'logic cone' mean in the context of FPGA?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
How to write the verilog code for a time borrowing latch?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What is time borrowing good for except solving hold time violation?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
The circuit design for 'carry out' signals seem to be wrong in this User Guide. Am I missing something?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
How and why would you use the latches in CLB in 7 series?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What are some better ways to improve this lengthy code?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What's the truth table of this block with the '-' symbol? How does the chain of '-' work?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
What's the truth table of this block with the '-' symbol? How does the chain of '-' work?
A subreddit for programmable hardware, including topics such as: * FPGA * CPLD * Verilog * VHDL
